1. What are the types of CORTEX-M series ?
2. How do you select a specific CORTEX-M processor ?
3. What is Trustzone System IP block ?
4. What is the use of T604 ? Have you used it ?
5. Have you come across LINARO ? Have you been involved in LINARO ?
6. What is pipeline shutdown ?
7. what are the kinds of protection available for SRAMS ?
How to use the single bit or double bit fault correction ?
8. What is interrupt pipelining ?
9. Explain the architecture of the CORTEX series ARM that you have used .
10. What is the use of the AMBA interface and where is it present in the architecture ?
11. What is branch prediction ?
12. What is out of order execution ? Have you considered it in selection of processor ?
13. If the pipleline is wider , the instruction throughput is high – True/False ?
14. What is the use of Neon Floating point engine ?
15. In what scenarios can neon do better than normal core ?
16. Is power dissipation more in neon compared to normal core ?
17. Incase of multimedia applications, what is the approximate number of times by which the throughput
is increased compared to normal core ?
18. Is Neon available with Cortex M or Cortex A series ?
19. Have you used RVDS ? Have you used gcc arm toolchain ? Which of these two tools is better ?
20. What is the use of –vectorize option ?
21. Have you used Palladium emulator ? Is it JTAG based ?
22. Have you used XDS510 emulator ?
23. What is Coresight System Trace Macrocell(STM) ?
24. What is the difference between ‘intrusive trace’ and ‘non-intrusive trace’ mechanisms ?
25. Which of the following is intrusive – printf, lttng, strace, ftrace, ltrace ?
26. Can you explain the flow from User application and the role of STM driver ?
27. What are the advantages and disadvantages of LTTng ?
28. What is hardware assisted instrumentation ?
29. What is the advantage of hardware assisted instrumentation over software instrumentation ?
30. What is PTM ?
31. What is TPIU ?
32. What is ITM ?
33. What is ETM ?
34. Low latency instrumentation is required for ISR tracing, Bootcode tracing . How is low latency
tracing achieved ?
35. STM cannot trace instructions. It traces only system level calls – True / False.
36. ETM is for data/program instructions & for cache/DMA level instructions – True / False.
37. In Kinetis, can SRAM be configured to act as either NVRAM or EEPROM ? Have you configured or tried it ?
38. How many power modes are there in Kinetis ? Can you tell the wakeup/recovery time for every mode ?
Which mode has the fastest recovery time ? Which mode has the lowest current consumption ?
39. Cortex M4 has Run , Sleep and Deep sleep modes – True / False ?
40. Is 32-pin Cortex M4 compatible with 256 pin Cortex M4 processor ?
41. What is I2S interface ?
42. What are the features of Cortex M4 ?
43. Tell about the Exception Handling in ARM processor. What does the ARM Core do automatically for every exception ?
44. Can you tell about DSP in ARM7TDMI or DSP in STRONGARM or DSP in ARM9E ?
45. Why should you design the DSP algorithm in general ARM architecture so that saturation is not required ?
46. Tell about AIF(Arm Image Format) and AOF(Arm Object Format) ?
47. What are the Memory initialization directives ?
48. What is the use of ‘SWI’ in ARM assembly ?
49. How to Represent a Digital Signal in ARM ?
50. Give Example of STMFD w.r.t Stack Operation push/pop ?
51. Tell about Extended Multiply Instructions in ARM
52. Tell about the NORMAL Multiply Instructions in ARM
53. Tell about ADR’s relation with LDR and the Advantage of using LDR together with ‘=’ ?
54. When does the Processor Stall in ARM and what is the pipeline hazard in ARM?
55. What is called ‘pipeline bubble’ in ARM ?
56. What is Saturating Arithmetic ? Explain
57. Tell the 2 software methods available to remove interlocks following load instructions
58. Tell about ‘Load Scheduling By Preloading’ and ‘Load Scheduling by unrolling’ ?
59. How will you flush the instuction Cache in ARM processor ?
60. List the issues when porting C code to the ARM processor ?
61. What are the advantages of writing in Assembly in ARM processor?
62. Explain this -> “AREA |.text|, CODE, READONLY”
63. What is the use of the ‘EXPORT’ directive ?
64. What is the use of various directives ?
65. How to build using command line tools w.r.t ARM ?
66. Write a simple square.s program in ARM assembly called from a C file ?
67. What will you change that program when calling ARM code from C compiled as Thumb ?
68. How will you allow Thumb C code to call the ARM assembly Code ?
69. What is the use of ‘RN’ directive in ARM assembly ?
70. What imports the libraries like printf automatically in the assembly side of ARM ?
71. What is the DCB directive and its relation with strings ?
72. What is ARMulator ? Where and How have you used it ?
73. How will you handle the Register Shortage problem in ARM ?
74. Relation between CPSR flags, S Suffix Instructions and Comparison Instructions ?
75. What is Conditional Execution in ARM ?
76. What is single issue multiple data (SIMD) processing ?
77. What is a Coprorcessor / CP15 in ARM ?
78. What does the ‘B’ mean in LDRB or What is the difference between LDR and LDRB in ARM ?
79. What is the use of Write-Back ?
80. When should i use ‘!’ in ARM programming and where is it Not Allowed to be used in ARM programming ?
81. Tell about ‘Single Data Transfer’ and ‘Multiple Data Transfer’ in ARM
82. How will you manually Enable / Disable an interrupt in ARM Processor ?
83. Tell about MRS and MSR instructions ?
84. Can you tell a 32-bit branch instruction and the way you used it ?
85. When have you used Thumb instructions in ARM processor ?
86. Write a program to mask bytes in ARM assembly ?
87. ARM7 family of processors does not use any branch prediction scheme. Neither
ARM9 nor ARM9E family implements branch prediction – True / False
88. The ARM11 micro-architecture uses two techniques to predict branches – True / False
89. What is Translation Lookaside Buffer (TLB) ?
90. What are the types of addressing modes in ARM ?
91. Can you brief up the evolution of ARM architecture ?
92. Why ARM7TDMI alone highlights the features that it supports in its naming and why not other ARM architectures ?
93. When will you choose to use ARM and when will you choose to use Thumb instructions ?
94. Can you explain the operation of ARM7 pipeline for simple instructions ?
95. Can you tell about function performed by this instruction – ADD r3, r5, r12 ?